Blocks of random access memories (RAMS), often called Block RAMs or BRAMs, are dedicated resources used for data storage in programmable logic devices (PLDs), such as Field Programmable Gate Arrays (FPGAs) or complex programmable logic devices (CPLDs). Block RAMS can have a variety of depths, output data widths for the output port, and input data widths for the input port. The ratio of the width of the output port to the input port is referred to as the aspect ratio. Some memory, including block RAMs, allow any aspect ratio that is a power of two (e.g., ½, 1, 2, 4 . . . ).
A typical memory with an aspect ratio of one works as expected. That is, whatever is written into the most significant bit (MSB) is read out as the MSB, with the remaining bits following. For example, if the input data width is four and ‘1000’ is written into the memory at address X, then ‘1000’ will be read from address X. In a conventional memory with an aspect ratio of greater than one, the address to which data is written can be controlled. That is, the user writes data over several cycles into specific addresses so that when the data is read out of the MEMORY, it will contain the correct bit in the MSB. However, such read/write operations become problematic when using sequential operations, such as first-in first-out (FIFO) memories, stacks, initialization, etc. For these special-purpose memories, the sequential operations to the memory may occur in a manner inconsistent with the structure of the memory, leading to incorrect ordering or corrupted data.
The example of FIG. 1 shows a write and a read operation using a conventional memory. Because the aspect ratio of the memory of FIG. 1 is greater than one (i.e. two in this case where the output width is four and the input width is two), the left side of the figure illustrates two write cycles and the right side illustrates one read cycle. With a 4-bit memory having a 2-bit input data bus, there are two sectors because to fill a 4-bit section would require two writes. The read operation shows the memory having a 4-bit output data bus. Because the 4-bit bus can read the entire section in one read, there is only one sector. When the sequence ‘ABCD’ is written into the memory in two write cycles, the first write places the MSB ‘A’ and the next bit ‘B’ into the memory. The second write places ‘C’ and the LSB ‘D’ into the memory. This data is read from the memory in one read cycle because the output port is 4-bits wide. Instead of reading ‘A’ as the MSB, ‘C’ is the first in the sequence. The sequence ‘CDAB’ is read out of the memory rather than the sequence ‘ABCD’. Accordingly, the data that was written into the memory is corrupted. This corruption occurs anytime that the aspect ratio is greater than one as a result of the intrinsic way that a conventional memory scales to handle ports with different aspect ratios.
FIG. 2, which shows the data addressing for all possible aspect ratios, further illustrates the problem of reading data when a memory has an aspect ratio which is greater than one. The first row illustrates the addressing of a memory if it was 1-bit wide and 16384 deep. The second row illustrates if the memory is 2-bits wide and 8192 deep. Using the example from FIG. 1, if ‘AB’ is written into the second row it would be placed in the 00 slot. ‘CD’ would then be placed in the 01 slot. The read operation is a 4-bit wide bus, which is demonstrated by the third row. It reads the data in the memory, putting slot 01 from the second row in the MSB and slot 00 from the second row in the LSB. Therefore, the sequence ‘CDAB’ is read from the memory instead of the sequence ‘ABCD’ which was written into the memory.
Accordingly, there is a need for an improved circuit for and method of outputting data from a memory having asymmetric input and output ports.